SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS
Title | SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS |
Publication Type | Journal Article |
Year of Publication | 2012 |
Authors | Zimmer, B., Toh S. Oon, Vo H., Lee Y., Thomas O., Asanović K., & Nikolic B. |
Published in | IEEE Transactions on Circuits and Systems-II |
Volume | 59 |
Issue | 12 |
Page(s) | 853-857 |
Other Numbers | 3458 |
Abstract | Reducing static random-access memory (SRAM) operationalvoltage (Vmin) can greatly improve energy efficiency,yet SRAM Vmin does not scale with technology due to increasedprocess variability. Assist techniques have been shown to improvethe operation of SRAM, but previous investigations of assist techniquesat design time have either relied on static metrics that donot account for important transient effects or make specific assumptionsabout failure distributions. This paper uses importancesampling of dynamic failure metrics to quantify and analyze theeffect of different assist techniques, array organization, and timingon Vmin at design time. This approach demonstrates that themost effective technique for reducing SRAM Vmin is the negativebitline write assist, resulting in a Vmin of 600 mV for a 28-nm LPprocess in the typical corner.Index TermsAssist techniques, importance sampling, lowvoltagestatic random-access memory (SRAM), SRAM |
URL | https://www.icsi.berkeley.edu/pubs/arch/ICSI_sramassisttechniques12.pdf |
Bibliographic Notes | IEEE Transactions on Circuits and Systems-II, Vol. 59, No. 12, pp. 853-857 |
Abbreviated Authors | B. Zimmer, S. O. Toh, H. Vo, Y. Lee, O. Thomas, K. Asanovi?, and B. Nikoli? |
ICSI Research Group | Architecture |
ICSI Publication Type | Article in journal or magazine |