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Monolithic Silicon Photonics for Processor-to-DRAM Interconnects
In a collaboration with the MIT Center for Integrated Photonic Systems,
researchers from the Architecture Group are exploring the use of silicon photonics for processor-to-memory interconnect. Projected advances in electrical signaling seem unlikely to fulfill the memory bandwidth demands of future manycore processor chips. Monolithic silicon photonics, which integrates optical components with electrical transistors in a conventional CMOS process, is a promising new technology that could provide large improvements in achievable interconnect bandwidth. In a DARPA-funded effort, the ICSI Architecture Group is exploring possible memory interconnect schemes to exploit the new photonic device and circuit technology being developed at MIT.
Maven (Malleable Array of Vector-thread ENgines)
In earlier work at MIT, Professor Asanovic's team developed the Scale vector-thread architecture and processor prototype, which combines data-level and thread-level parallel execution models in a single unified architecture.
MAVEN is the second-generation vector-thread architecture, designed to scale up to hundreds of execution lanes, and with the goal of providing very high throughput at low energy for a wide variety of parallel applications.
MAVEN is based on a new compact lane design, which is replicated to yield a "sea of lanes" execution substrate. At run-time, lanes are ganged together to form variable-sized vector-thread engines, sized to match application needs.
More about the Architecture Research Group >>
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