Designing Chip-Level Nanophotonic Interconnection Networks
Title | Designing Chip-Level Nanophotonic Interconnection Networks |
Publication Type | Journal Article |
Year of Publication | 2012 |
Authors | Batten, C., Joshi A., Stojanovic V., & Asanović K. |
Published in | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
Volume | 2 |
Issue | 2 |
Page(s) | 137-153 |
Other Numbers | 3455 |
Abstract | Technology scaling will soon enable high-performanceprocessors with hundreds of cores integrated onto a singledie, but the success of such systems could be limited by thecorresponding chip-level interconnection networks. There havebeen many recent proposals for nanophotonic interconnectionnetworks that attempt to provide improved performance andenergy-ef |
URL | https://www.icsi.berkeley.edu/pubs/arch/ICSI_designingchiplevel12.pdf |
Bibliographic Notes | IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 2, pp. 137-153 |
Abbreviated Authors | C. Batten, A. Joshi, V. Stojanovi?, and K. Asanovi? |
ICSI Research Group | Architecture |
ICSI Publication Type | Article in journal or magazine |