Found 68 results
Author Title [ Type(Desc)] Year
Filters: Author is Krste Asanović  [Clear All Filters]
Asanović, K. (2018).  From T0 and CNS-1 to RISC-V and AI Hardware. 30 Years of Innovation: ICSI 30th Anniversary Celebration.
Technical Report
Asanović, K., Beck J., Callahan T. J., Feldman J., Irissou B., Kingsbury B., et al. (1993).  CNS-1 Architecture Specification: A Connectionist Network Supercomputer.
Morgan, N., Asanović K., Kingsbury B., & Wawrzynek J. (1990).  Developments in Digital VLSI Design for Artificial Neural Networks.
Asanović, K., & Morgan N. (1991).  Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks.
Asanović, K., Kingsbury B., Morgan N., & Wawrzynek J. (1991).  HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
Bilmes, J. A., Asanović K., Chin C-W., & Demmel J. (1998).  The PHiPAC v1.0 Matrix-Multiply Distribution..
Kingsbury, B., Irissou B., Asanović K., Wawrzynek J., & Morgan N. (1991).  Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks.
Waterman, A., Lee Y., Patterson D., & Asanović K. (2011).  The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA.
Batten, C., Krashinsky R., & Asanović K. (2007).  Scale Control Processor Test-chip.
Beamer, S., Asanović K., & Patterson D. (2011).  Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500.
Asanović, K., Beck J., Kingsbury B., Kohn P., Morgan N., & Wawrzynek J. (1991).  SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations.
Asanović, K., & Beck J. (1996).  T0 Engineering Data.
Asanović, K., & Johnson D. (1996).  Torrent Architecture Manual.