Publications

Found 16 results
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Filters: Author is Krste Asanović  [Clear All Filters]
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A
Asanović, K., Kingsbury B., Morgan N., & Wawrzynek J. (1991).  HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training.
Asanović, K., & Morgan N. (1991).  Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks.
Asanović, K., Beck J., Kingsbury B., Kohn P., Morgan N., & Wawrzynek J. (1991).  SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations.
Asanović, K., Beck J., Callahan T. J., Feldman J., Irissou B., Kingsbury B., et al. (1993).  CNS-1 Architecture Specification: A Connectionist Network Supercomputer.
Asanović, K., & Johnson D. (1996).  Torrent Architecture Manual.
Asanović, K., & Beck J. (1996).  T0 Engineering Data.
Asanović, K., Beck J., Johnson D., Kingsbury B., Morgan N., & Wawrzynek J. (1998).  Training Neural Networks with SPERT-II. 345-364.
Asanović, K., Beck J., Feldman J., Morgan N., & Wawrzynek J. (1993).  Designing a Connectionist Network Supercomputer. International Journal of Neural Systems.
Asanović, K. (1998).  Vector processing system with multi-operation, run-time configurable pipelines.
Asanović, K., & Witchel E.. (2007).  System and technique for fine-grained computer memory protection.
Asanović, K. (2007).  Transactors for Parallel Hardware and Software Co-design. Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007). 140-142.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., & Wittig R.. (2010).  Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California. IEEE Micro. 30(2), 5-6.
Asanović, K. (2018).  From T0 and CNS-1 to RISC-V and AI Hardware. 30 Years of Innovation: ICSI 30th Anniversary Celebration.