Publications

Found 116 results
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Weaver, N., & Sommer R. (2007).  Stress Testing Cluster Bro. Proceedings of USENiX DETER Community Workshop on Cyber Security Experimentation and Test (DETER 2007).
Weaver, N., Paxson V., Staniford S., & Cunningham R. (2003).  Large Scale Malicious Code: A Research Agenda.
Weaver, N. (2010).  Unencumbered by Success: The Usenix Security Grand Challenge Competition.
Weaver, N., Staniford S., & Paxson V. (2004).  Very Fast Containment of Scanning Worms. Proceedings of the 13th USENIX Security Symposium. 29-44.
Weaver, N., Paxson V., Staniford S., & Cunningham R. (2003).  A Taxonomy of Computer Worms. Proceedings of the ACM CCS First Workshop on Rapid Malcode (WORM 2003). 11-18.
Weaver, N., Staniford S., & Paxson V. (2007).  Very Fast Containment of Scanning Worms, Revisited. 113-145.
Weaver, N., Kreibich C., Dam M., & Paxson V. (2014).  Here Be Web Proxies. 8362, 183-192.
Weaver, N. (2018).  Risks of Cryptocurrencies. Communications of the ACM. 61(6), 20-24.
Weaver, N. (2009).  Peer to Peer Edge Caches Should Be Free.
Weaver, N., Hamadeh I.., Kesidis G.., & Paxson V. (2004).  Preliminary Results Using ScaleDown to Explore Worm Dynamics. Proceedings of the ACM Workshop on Rapid Malcode (WORM 2004).
Weaver, N., & Paxson V. (2004).  A Worst-Case Worm. Proceedings of Third Annual Workshop on Economics and Information Security (WEIS04).
Weaver, N., Sommer R., & Paxson V. (2009).  Detecting Forged TCP Reset Packets.
Weaver, N., Markovskiy Y., Patel Y., & Wawrzynek J. (2003).  Post Placement C-Slow Retiming for the Xilinx Virtex FPGA.
Weaver, N., & Wawrzynek J. (2000).  A Comparison of the AES Candidates Amenability to FPGA Implementation.
Weaver, N., Paxson V., & Gonzalez J. Maria (2007).  The Shunt: An FPGA-Based Accelerator for Network Intrusion Prevention. Proceedings of International Symposium on Field Programmable Gate Arrays (FPGA 2007). 199-206.
Weaver, N., Kreibich C., & Paxson V. (2011).  Redirecting DNS for Ads and Profit.
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1995).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. Proceedings of the Advances in Neural Information Processing Systems 8 Conference (NIPS 8). 619-625.
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1996).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. IEEE Computer. 29(3), 79-86.
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
Waterman, A. (2011).  Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed.
Waterman, A., Lee Y., Patterson D., & Asanović K. (2011).  The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA.
Waterman, A. (2011).  Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed.
Warren, W. (2000).  Global Posterior Probability Estimates as Decision Confidence Measures in an Automatic Speech Recognition System.
Warren, W. (2001).  Global Posterior Probability Estimates as Confidence Measures in an Automatic Speech Recognition System. Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2001).
Wang, D., Mahoney M. W., Mohan N., & Rao S. (2015).  Faster Parallel Solver for Positive Linear Programs via Dynamically-Bucketed Selective Coordinate Descent.

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