Publications

Found 68 results
Author Title [ Type(Asc)] Year
Filters: Author is Krste Asanović  [Clear All Filters]
Journal Article
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1996).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. IEEE Computer. 29(3), 79-86.
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
Krashinsky, R., Batten C., & Asanović K. (2008).  Implementing the Scale Vector-Thread Processor. ACM Transactions on Design Automation of Electronic Systems. 13(3), 
Asanović, K., & Wittig R.. (2010).  Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California. IEEE Micro. 30(2), 5-6.
Lee, J. W., Ng M. Cheuk, & Asanović K. (2012).  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. Journal of Parallel and Distributed Computing. 72(11), 1401-1411.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
Asanović, K., Beck J., Feldman J., Morgan N., & Wawrzynek J. (1993).  Designing a Connectionist Network Supercomputer. International Journal of Neural Systems.
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2009).  Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro. 29(4), 8-21.
Heo, S., Krashinsky R., & Asanović K. (2007).  Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. IEEE Transactions on VLSI Systems. 15(9), 1060-1064.
Conference Paper
Asanović, K. (2007).  Transactors for Parallel Hardware and Software Co-design. Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007). 140-142.
Liu, R., Klues K., Bird S., Hofmeyr S., Asanović K., & Kubiatowicz J. D. (2009).  Tessellation: Space-Time Partitioning in a Manycore Client OS.
Colmenares, J. A., Eads G., Hofmeyr S., Bird S., Moretó M., Chou D., et al. (2013).  Tessellation: Refactoring the OS around Explicit Resource Containers with Continuous Adaptation.
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1995).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. Proceedings of the Advances in Neural Information Processing Systems 8 Conference (NIPS 8). 619-625.
Joshi, A., Batten C., Kwon Y-J., Beamer S., Shamim I., Asanović K., et al. (2009).  Silicon-Photonic Clos Networks for Global On-Chip Communication. 124-133.
Paxson, V., Asanović K., Dharmapurikar S., Lockwood J.., Pang R., Sommer R., et al. (2006).  Rethinking Hardware Support for Network Analysis and Intrusion Prevention. Proceedings of the First USENIX Workshop on Hot Topics in Security (HotSec '06).
Colmenares, J. A., Bird S., Cook H., Pearce P., Zhu D.., Shalf J., et al. (2010).  Resource Management in the Tessellation Manycore OS.
Beamer, S., Sun C.., Kwon Y-J., Joshi A., Batten C., Stojanovic V., et al. (2010).  Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics. 129-140.
Colmenares, J. A., Saxton I., Battenberg E., Avižienis R., Peters N., Asanović K., et al. (2011).  Real-Time Musical Applications on an Experimental Operating System for Multi-Core Processors.
Tan, Z., Waterman A., Avižienis R., Lee Y., Cook H., Patterson D., et al. (2010).  RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors.
Jones, C.. G., Liu R., Meyerovich L.., Asanović K., & Bodik R. (2009).  Parallelizing the Web Browser.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., & Asanović K. (2009).  Manycore Processor Networks with Monolithic Integrated CMOS Photonics.
Pan, H., Hindman B., & Asanović K. (2009).  Lithe: Enabling Efficient Composition of Parallel Libraries.
Cook, H., Moretó M., Bird S., Dao K., Patterson D., & Asanović K. (2013).  A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness.
Maas, M., Reames P., Morlan J., Asanović K., Joseph A. D., & Kubiatowicz J. D. (2012).  GPUs: An Opportunity for Offloading Garbage Collection.

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