Publications
SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training.
IEEE Computer. 29(3), 79-86.
(1996). RAMP: Research Accelerator for Multiple Processors.
IEEE Micro. 27(2), 46-57.
(2007). Implementing the Scale Vector-Thread Processor.
ACM Transactions on Design Automation of Electronic Systems. 13(3),
(2008). Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California.
IEEE Micro. 30(2), 5-6.
(2010). Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.
Journal of Parallel and Distributed Computing. 72(11), 1401-1411.
(2012). Designing Chip-Level Nanophotonic Interconnection Networks.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
(2012). Designing Chip-Level Nanophotonic Interconnection Networks.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
(2012). Designing a Connectionist Network Supercomputer.
International Journal of Neural Systems.
(1993). Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.
IEEE Micro. 29(4), 8-21.
(2009). Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
IEEE Transactions on VLSI Systems. 15(9), 1060-1064.
(2007). Transactors for Parallel Hardware and Software Co-design.
Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007). 140-142.
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(2009).
(2013). SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training.
Proceedings of the Advances in Neural Information Processing Systems 8 Conference (NIPS 8). 619-625.
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(2009). Rethinking Hardware Support for Network Analysis and Intrusion Prevention.
Proceedings of the First USENIX Workshop on Hot Topics in Security (HotSec '06).
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