Found 68 results
Author Title [ Type(Desc)] Year
Filters: Author is Krste Asanović  [Clear All Filters]
Conference Paper
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2008).  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. 21-30.
Tan, Z., Waterman A., Cook H., Bird S., Asanović K., & Patterson D. (2010).  A Case for FAME: FPGA Architecture Model Execution. 290-301.
Vo, H., Lee Y., Waterman A., & Asanović K. (2013).  A Case for OS-Friendly Hardware Accelerators.
Bachrach, J., Vo H., Richards B., Lee Y., Waterman A., Avižienis R., et al. (2012).  Chisel: Constructing Hardware in a Scala Embedded Language.
Hampton, M.., & Asanović K. (2008).  Compiling for Vector-Thread Architectures. 205-215.
Pan, H., Hindman B., & Asanović K. (2010).  Composing Parallel Software Efficiently with Lithe. 376-387.
Tiwari, M., Mohan P., Osheroff A., Alkaff H., Shi E., Love E., et al. (2012).  Context-Centric Security.
Lee, J. W., King M.., & Asanović K. (2007).  Continual Hashing for Efficient Fine-Grain State Inconsistency Checking. 33-40.
Lee, Y., Krashinsky R., Grover V., Keckler S. W., & Asanović K. (2013).  Convergence and Scalarization for Data-Parallel Architectures.
Tan, Z., Asanović K., & Patterson D. (2011).  Datacenter-Scale Network Research on FPGAs.
Beamer, S., Asanović K., Batten C., Joshi A., & Stojanovic V. (2009).  Designing Multi-Socket Systems Using Silicon Photonics. 521-522.
Beamer, S., Asanović K., & Patterson D. (2012).  Direction-Optimizing Breadth-First Search.
Beamer, S., Buluç A., Asanović K., & Patterson D. (2013).  Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search.
Lee, Y., Avižienis R., Bishara A.., Xia R.., Lockhart D.., Batten C., et al. (2011).  Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators. 129-140.
Tan, Z., Asanović K., & Patterson D. (2008).  An FPGA Host-Multithreaded Functional Model for SPARC v8.
Lee, J. W., Ng A.., & Asanović K. (2008).  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. 89-100.
Maas, M., Reames P., Morlan J., Asanović K., Joseph A. D., & Kubiatowicz J. D. (2012).  GPUs: An Opportunity for Offloading Garbage Collection.
Cook, H., Moretó M., Bird S., Dao K., Patterson D., & Asanović K. (2013).  A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness.
Pan, H., Hindman B., & Asanović K. (2009).  Lithe: Enabling Efficient Composition of Parallel Libraries.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., & Asanović K. (2009).  Manycore Processor Networks with Monolithic Integrated CMOS Photonics.
Jones, C.. G., Liu R., Meyerovich L.., Asanović K., & Bodik R. (2009).  Parallelizing the Web Browser.
Tan, Z., Waterman A., Avižienis R., Lee Y., Cook H., Patterson D., et al. (2010).  RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors.
Colmenares, J. A., Saxton I., Battenberg E., Avižienis R., Peters N., Asanović K., et al. (2011).  Real-Time Musical Applications on an Experimental Operating System for Multi-Core Processors.